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PACVGA203 VGA Port Companion Circuit
Features
* * * * * * * * * Single-chip solution for the VGA port interface Includes ESD protection, level shifting, and RGB termination Seven channels of ESD protection for all VGA port connector pins, meeting IEC-61000-4-2 Level-4 ESD requirements (8kV contact discharge) Very low loading capacitance from ESD protection diodes on VIDEO lines; 4pF typical 75 termination resistors for VIDEO lines (matched to 1% typ.) TTL to CMOS level-translating buffers with powerdown mode for HSYNC and VSYNC lines Bi-directional level shifting N-channel FETs provided for DDC_CLK & DDC_DATA channels Compact 24-pin QSOP package Lead-free version available
Product Description
The PACVGA203 incorporates seven channels of ESD protection for all signal lines commonly found in a VGA port. ESD protection is implemented with current steering diodes designed to safely handle the high surge currents encountered with IEC-61000-4-2 Level4 ESD Protection (8kV contact discharge). When a channel is subjected to an electrostatic discharge, the ESD current pulse is diverted via the protection diodes into either the positive supply rail or ground where it may be safely dissipated. Separate positive supply rails are provided for the VIDEO, DDC and SYNC channels to facilitate interfacing with low voltage Video Controller ICs and provide design flexibility in multisupply-voltage environments. Two non-inverting drivers provide buffering for the HSYNC and VSYNC signals from the Video Controller IC (SYNC_IN1, SYNC_IN2). These buffers accept TTL input levels and convert them to CMOS output levels that swing between Ground and VCC4 (cont'd next page).
Applications
* * Notebook computers with VGA port Desktop PCs with VGA port
Simplified Electrical Schematic
VCC2 12 GNDD VIDEO_1 VIDEO_2 VIDEO_3 3 4 5 GNDD 6 VCC2 GNDD TERM_1 TERM_2 TERM_3 GNDA 8 9 10 7 GNDA 75 75 75 DDC_IN2 GNDD 17 RC 18 DDC_OUT2 SYNC_IN2 GNDD GNDD GNDD GNDD 21 24 SD2 VCC3 GNDD RC VCC4 1 GNDD 22 RS SYNC_OUT2 GNDD DDC_IN1 16 RC 15 DDC_OUT1 RB GNDD GNDD 11 SYNC_IN1 19 23 SD1
VCC1 2
VCC3 14
V_BIAS 13
D1
VCC4 1
20 RS
SYNC_OUT1
GNDD
PWR_UP
(c) 2004 California Micro Devices Corp. All rights reserved. 12/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
1
PACVGA203
Product Description (cont'd)
These drivers have nominal 15 output impedance (RS) which can be combined with an external resistor to match the characteristic impedance of the HSYNC & VSYNC lines of the video cables typically used in PC applications. Two N-channel FETs provide the level shifting function required when the DDC controller is operated at a lower supply voltage than the monitor. Three 75 resistors suitable for terminating the video signals from the video DAC are also provided. These resistors have separate input pins to allow insertion of additional EMI filtering, if required, between the termination point and the ESD protection diodes. These resistors are matched to better than 2% for excellent signal level matching of the R/G/B signals. When the PWR_UP input is driven LOW, the SYNC inputs can be floated without causing the SYNC buffers to draw any current from the VCC4 supply. When the PWR_UP input is LOW the SYNC outputs are driven LOW. VCC3 can be derived from VCC4, if desired, by connecting VCC3 to V_BIAS. In applications where VCC4 may be powered down, diode D1 blocks any DC current paths from the DDC_OUT pins back to the powered down VCC4 rail via the top ESD protection diodes. The PACVGA203 device is housed in a 24-pin QSOP package and is available with optional lead-free finishing.
PACKAGE / PINOUT DIAGRAM
Top View
VCC4 VCC1 VIDEO_1 VIDEO_2 VIDEO_3 GNDD GNDA TERM_1 TERM_2 TERM_3 PWR_UP VCC2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SD2 SD1 SYNC_OUT2 SYNC_IN2 SYNC_OUT1 SYNC_IN1 DDC_OUT2 DDC_IN2 DDC_IN1 DDC_OUT1 VCC3 V_BIAS
Note: This drawing is not to scale.
24-pin QSOP
Ordering Information
PART NUMBERING INFORMATION
Standard Finish Pins 24 Package QSOP-24 Ordering Part Number1 PACVGA203Q Part Marking PACVGA203Q Lead-free Finish Ordering Part Number1 PACVGA203QR Part Marking PACVGA203QR
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
(c) 2004 California Micro Devices Corp. All rights reserved.
2
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
12/07/04
PACVGA203
PIN DESCRIPTIONS
LEAD(s) 1 2 3-5 6 7 8-10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NAME VCC4 VCC1 VIDEO_1, VIDEO_2, VIDEO_3 GNDD GNDA TERM_1, TERM_2, TERM_3 PWR_UP VCC2 V_BIAS VCC3 DDC_OUT1 DDC_IN1 DDC_IN2 DDC_OUT2 SYNC_IN1 SYNC_OUT1 SYNC_IN2 SYNC_OUT2 SD1 SD2 DESCRIPTION Positive voltage supply pin. This is an isolated VCC pin for the SYNC_1, SYNC_2, SD1 and SD2 circuits. Positive voltage supply pin. This is an isolated VCC pin for the VIDEO_1, VIDEO_2 and VIDEO_3 ESD circuits. RGB Video Protection Channels. These pins tie to the RGB video lines (for example, the Blue signal) between the VGA controller device and the video connector. Digital Ground reference supply pin. Ground reference supply pin for TERM_1, TERM_2 and TERM_3 pins. RGB Video Termination Channels. These pins tie to the RGB video lines (for example, the Blue signal) providing a 75 termination to GNDA for the given video channel. Sync Signal Output 1. Ties to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Positive voltage supply pin. This is an isolated VCC pin for the DDC_IN1 and DDC_IN2 input circuits. Defines the logic one level for the DDC_OUTn outputs. Used to derive VCC3 from VCC4 input. Positive voltage supply pin. This is an isolated VCC pin for the DDC_OUT1 and DDC_OUT2 ESD protection circuits. DDC Signal Output 1. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). DDC Signal Input 1. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Data serial line). DDC Signal Input 2. Connects to the VGA Controller side of one of the DDC signals (for example, the bidirectional DDC_Clk). DDC Signal Output 2. Connects to the connector side of one of the DDC signals (for example, the bidirectional DDC_Clk). Sync Signal Buffer Input 1. Connects to the VGA Controller side of one of the sync lines (for example, the Horizontal Sync signal). Sync Signal Buffer Output 1. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal). Sync Signal Buffer Input 2. Connects to the VGA Controller side of one of the sync lines (for example, the Vertical Sync signal). Sync Signal Buffer Output 2. Connects to the video connector side of one of the sync lines (for example the Vertical Sync signal). Sync Signal Filter 1. Connects to the video connector side of one of the sync lines (for example the Vertical Sync signal). Sync Signal Filter 2. Connects to the video connector side of one of the sync lines (for example the Horizontal Sync signal).
(c) 2004 California Micro Devices Corp. All rights reserved. 12/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
3
PACVGA203
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER VCC1,VCC2,VCC3, and VCC4 Supply Voltage Diode D1 Forward DC Current Operating Temperature Range Storage Temperature Range DC Voltage at Inputs VIDEO_1, VIDEO_2, VIDEO_3 TERM_1, TERM_2, TERM_3 DDC_IN1, DDC_IN2 DDC_OUT1, DDC_OUT2 SYNC_IN1, SYNC_IN2 Package Power Rating RATING [GND - 0.5] to +6.0 100 -40 to +85 -65 to +150 (GND - 0.5) to (VCC1 + 0.5) -6.0, +6.0 (GND - 0.5) to (VCC2 + 0.5) (GND - 0.5) to (VCC3 + 0.5) (GND - 0.5) to (VCC4 + 0.5) 1000 UNITS V A C C V V V V V mW
STANDARD OPERATING CONDITIONS
PARAMETER Operating Temperature Range RATING 0 to +70 UNITS C
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
SYMBOL ICC1 ICC2, ICC3 ICC4 PARAMETER VCC1 Supply Current VCC2 & VCC3 Supply Current VCC4 Supply Current CONDITIONS VCC1 = 5.0V, VIDEO inputs at VCC1 or GND level VCC2 = VCC3 = 5.0V VCC4 = 5.0V; SYNC inputs at GND or VCC4 level; PWR-UP pin at VCC4; SYNC outputs unloaded VCC4 = 5.0V; SYNC inputs at 3.0V; PWR-UP pin at VCC4; SYNC outputs unloaded VCC4 = 5.0V; PWR-UP input at GND; SYNC outputs unloaded VBIAS RT VBIAS Open Circuit Voltage Video Termination Resistance RT Resistance Matching No external current drawn from VBIAS pin 71.25 VCC4-0.8 75 1 78.75 2 10 MIN TYP MAX 10 10 UNITS A A A
200 10
A A V %
(c) 2004 California Micro Devices Corp. All rights reserved.
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430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
12/07/04
PACVGA203
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1) (CONT'D)
SYMBOL VIH VIL VOH VOL ROH ROL RB,RP RC IN Resistor Value VCC2 Pull-down Resistor Value PWR_UP = VCC3 = 5.0V VCC2 = 3.0V 0.5 0.5 PARAMETER Logic High Input Voltage Logic Low Input Voltage Logic High Output Voltage Logic Low Output Voltage Output Resistance CONDITIONS VCC4 = 5.0V; See Note 2 VCC4 = 5.0V; See Note 2 IOH = -4mA, VCC4 = 5.0V; See Note 2 IOL = 4mA, VCC4 = 5.0V; See Note 2 See Note 2 4.94 0.06 15 15 1.0 1.5 2.0 3.0 MIN 2.0 0.8 TYP MAX UNITS V V V V M M
Input Current VIDEO inputs VCC1= 5.0V; VIN = VCC1 or GND HSYNC, VSYNC inputs VCC4 = 5.0V; VIN = VCC4 or GND Off-state Leakage Current, Level-shifting NFET Voltage drop across level shifting NFET when turned ON Input Capacitance VIDEO_1,VIDEO_2 & VIDEO_3 inputs SYNC Drivers L => H Propagation Delay SYNC Drivers H => L Propagation Delay SYNC Drivers Output Rise & Fall Times ESD Withstand Voltage (VCC2 - VDDC_IN) < 0.4V; VDDC_OUT = VCC2 (VCC2 - VDDC_OUT) < 0.4V; VDDC_IN = VCC2 VCC2= 2.5V; VS = GND; IDS = 3mA
+1 +1 10 10 0.15
A A A A V
IOFF VON
CIN
Note 4 applies for all cases; VCC1 = 5.0V; VIN = 2.5V; measured at 1MHz VCC1 = 2.5V; VIN = 1.25V; measured at 1MHz CL = 50pF; VCC=5.0V,Input tR and tF < 5ns CL = 50pF; VCC=5.0V; Input tR and tF < 5ns CL = 50pF; VCC=5.0V; Input tR and tF < 5ns (measured 10% - 90%) VCC1 = VCC3 = VCC4 = 5V; Notes 3 & 4
3.0 3.0
4.0 4.5 8.0 8.0
5.0 5.6 12.0 12.0 10.0
pF pF ns ns ns kV
tPLH tPHL tR, tF VESD
5.0 8
7.0
Note 1: All parameters specified over standard operating conditions unless otherwise noted. Note 2: This parameter applies only to the HSYNC and VSYNC channels. HSYNC and VSYNC have 24mA drivers with RS added in series to terminate transmission line. Note 3: Per the IEC-61000-4-2 International ESD Standard, Level 4 contact discharge method. VCC1, VCC3 and VCC4 must be bypassed to GND via a low impedance ground plane with a 0.2uF, low inductance, chip ceramic capacitor at each supply pin. ESD pulse is applied between the applicable pins and GND. ESD pulse can be positive or negative with respect to GND. Applicable pins are: VIDEO_1, VIDEO_2, VIDEO_3, SD1, SD2, DDC_OUT1 and DDC_OUT2. All other pins are ESD protected to the industry standard 2kV per the Human Body Model (MIL-STD-883, Method 3015). Note 4: This parameter is guaranteed by design and characterization.
(c) 2004 California Micro Devices Corp. All rights reserved. 12/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
5
PACVGA203
Test Circuit Information
Average Current through VCC4 (ICC4) The circuit in Figure 1 was used to characterize ICC4 current as SYNC_IN signal frequency varies. A square wave signal was connected to the input of one of the SYNC buffers (i.e. pin 19 or pin 21). The frequency of this signal was varied between 0 and 100 kHz. The risetime and falltime was kept constant at 10ns. Three different values of C1 were used: 0pF, 50pF and 100pF. The results are plotted in Figure 2.
VCC4 +5V
ICC4 3.3V 0V SYNC_IN SYNC_OUT C1
Figure 1. Sync Buffer ICC4 Test Circuit
100 90 80 70
ICC4 vs. SYNC_IN Frequency
ICC4, uA
60 50 40 30 20 10 0 0 20 40 60 80 100 Frequency, kHz 100pF 50pF 0pF
Figure 2. ICC4 vs. SYNC_IN Frequency Performance Data
(c) 2004 California Micro Devices Corp. All rights reserved.
6
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
12/07/04
PACVGA203
Application Information
DDC_VCC VIDEO_DAC_VCC
0.2uF 0.2uF 0.2uF 0.2uF
12 2 14 13
5V
GNDD
GNDD
VCC2 VCC1
16 17
VCC3 V_BIAS VCC4 PWR_UP 11 DDC_OUT1 15 DDC_OUT2 18 SYNC_OUT1 22 SYNC_OUT2
20 1
DDC_Data DDC_Clk
DDC_IN1 DDC_IN2 SYNC_IN1 SYNC_IN2 TERM_1 TERM_2 TERM_3
Video Controller
H-Sync V-Sync Red Grn Blue
VF** VF** VF**
19 21
Video Connector
SR*
R1
R2
DDC_Data DDC_Clk
8 9 10
SR* SF** SF**
PACVGA203
3 4 5
VF** - VIDEO EMI Filter SF** - SYNC EMI Filter SR* - external resistor to match video cable characteristic impedance.
VIDEO_1 VIDEO_2 VIDEO_3 GNDA
7
SD1 23 24 SD2
H-Sync V-Sync
GNDD
6
R G B
Figure 3. Typical Connection Diagram A resistor may be necessary between the VCC3 pin and ground if protection against a stream of ESD pulses is required while the PACVGA203 is in the power-down state. The value of this resistor should be chosen such that the extra charge deposited into the VCC3 bypass capacitor by each ESD pulse will be discharged before the next ESD pulse occurs. The maximum ESD repetition rate specified by the IEC-61000-4-2 standard is one pulse per second. When the PACVGA203 is in the power-up state, an internal discharge resistor is connected to ground via an FET switch for this purpose. For the same reason, VCC1 and VCC4 may also require bypass capacitor discharging resistors to ground if there are no other components in the system to provide a discharge path to ground. GNDA, the reference voltage for the 75 resistors is not connected internally to GNDD and should ideally be connected to the ground of the video DAC IC.
(c) 2004 California Micro Devices Corp. All rights reserved. 12/07/04
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
7
PACVGA203
Mechanical Details
QSOP Mechanical Specifications: PACVGA203 devices are packaged in 24-pin QSOP packages. Dimensions are presented below. For complete information on the QSOP-24 package, see the California Micro Devices QSOP Package Information document. Mechanical Package Diagrams
TOP VIEW
D
24 23 22 21 20 19 18 17 16 15 14 13
PACKAGE DIMENSIONS
Package Pins Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.35 0.10 0.20 0.18 8.56 3.81 5.79 0.40 Max 1.75 0.25 0.30 0.25 8.73 3.98 6.19 1.27 Min 0.053 0.004 0.008 0.007 0.337 0.150 0.228 0.016 QSOP (JEDEC name is SSOP) 24 Inches Max 0.069 0.010 0.012 0.010 0.344 0.157 0.244 0.050
C
END VIEW SEATING PLANE SIDE VIEW 1 2 3 4 5 6 7 8 9 10 11 12
H
Pin 1 Marking
E
A B e
A1
0.64 BSC
0.025 BSC
55 pcs* 2500 pcs Controlling dimension: inches
L
* This is an approximate number which may vary.
Package Dimensions for QSOP-24
(c) 2004 California Micro Devices Corp. All rights reserved.
8
430 N. McCarthy Blvd., Milpitas, CA 95035-5112
Tel: 408.263.3214
Fax: 408.263.7846
www.calmicro.com
12/07/04

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